With continuous advancements in the semiconductor industry, transistors with smaller than 20 nm feature size have enabled the integration of multi-billion transistors on a single die. With the failure of MOSFET scaling however, only a fraction of the transistors on a die can operate at full voltage/frequency to not exceed the thermal design power (TDP). A large proportion of the circuit blocks is either inactive (dark silicon) or in a reduced-power state (dim silicon) at any given time to satisfy the power and thermal constraints. Despite the significant amount of research and growing necessity for a holistic power optimization technique, existing efforts to minimize power dissipation are typically not coherent. The existing research efforts are disjointed into two pieces: 1) the dynamic and static power loss at the load circuits is minimized or 2) the power loss during power-conversion is minimized.
There is a growing trend for integrating the voltage regulators fully on-chip to improve the quality of voltage delivered to the load circuits. Voltage regulators are typically designed to provide the highest power-conversion efficiency when delivering a particular output current regime, typically the maximum current for LDO (low-dropout) and SC (switched capacitor) regulators. Since dynamically changing the design parameters of a voltage regulator under different workloads is difficult, existing power management techniques suffer from increased voltage conversion losses during idle states when the current demand is low and regulator efficiency is reduced.
In modern mobile platforms, more than 32% of the overall battery power is dissipated during high-to-low voltage conversion before the power even reaches the load circuits. The primary reason for this huge power loss is that power delivery networks are designed to satisfy the stringent noise requirements under worst-case loading conditions, which is typically the full utilization of the overall chip computing and memory resources when the current demand is the highest.
Parallel voltage regulation has been widely used for buck and SC regulators to reduce the output voltage ripple by interleaving multiple regulators with phase shifted switching frequencies. Advantages of interleaved regulation include reduced filter size for buck converters, improved load response, and higher efficiency. The interleaved architectures, however, have not been exploited until recently to regulate voltage close to the load circuits to minimize noise. Distributed on-chip voltage regulation is an emerging research area where multiple voltage regulators are connected in parallel, delivering current to the same power network close to the load circuits. Although challenges such as device mismatch, offset voltages among parallel regulators, overall system stability, and balanced current sharing need to be considered, distributed voltage regulation can provide sub-nanosecond load regulation to attain high performance under increased temporal and spatial workload variations in modem ICs. Aggressive power saving mechanisms are currently implemented as a result of the modem ICs exhibiting frequent idle periods. It is projected that more than half of the circuit needs to be idle at 8 nm technology node to satisfy the TDP requirement in server processors or to improve the battery life in mobile processors.
Design-for-power has become one of the primary objectives resulting from the continuous demand to improve the battery life of mobile devices or to minimize the cooling costs of servers. To save power and mitigate thermal emergencies, circuits typically enter reduced power states when the workload is light. Prior art voltage regulators, however, operate indifferently under varying workload conditions due to a lack of different operating modes. When a prior art voltage regulator is optimized for a particular load current, significant power is dissipated during voltage conversion while delivering power to a different load current than the load current for which the voltage regulator is optimized.
Accordingly, what is needed in the art is an improved system and method for voltage conversion efficiency at different utilization levels for on-chip voltage regulators.